1. Technical Field
The present invention relates a semiconductor device and a method of manufacturing the same. More specifically, it relates a method of forming a source and/or a drain of a transistor element by ion implantation and its structure.
2. Related Arts
Recently, shallow trench isolation (STI) has been adapted to an element isolation region accompanied with miniaturization of a transistor size formed on a silicon substrate. A STI structure includes a trench in a semiconductor substrate and a silicon oxide film within it, yielding in a potential stress between an active region for a transistor element and a silicon oxide film in the STI.
When an impurity is doped into an active region in a silicon substrate by an ion implantation method for forming a source and/or a drain, the interface between the STI region and the active region receives damages by ion implantation. In order to release such potential stress, a defect such as dislocation in active region side, namely pure crystalline silicon substrate is yielded.
In such case, many of these defects cause defects of electric properties such as increase of leak current and decrease of break down voltage, when a transistor element is turned on.
In order to solve this issue, as shown in the Japanese Unexamined Patent Publication 2003-229496 for example, ion implantation is implemented by protecting a STI region and it's adjacent active region with a mask and anneal processing is performed thereafter so that a source and/or a drain region is formed by diffusing impurities with in a active region in which an ion is not doped by ion implantation.
In a method of forming a source and a drain by annealing process, which diffuses impurities into a non-doped active region, however, it is difficult control concentration distribution of impurities in a source and/or a drain, if such source and/or drain is formed by lightly doped drain (LDD). Further, it should be avoided to diffuse impurities into the inside of a substrate. A source and/or a drain are insufficiently formed when annealing is not preformed, making a transistor element not operate as initially designed.